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december 2007 rev 7 1/71 1 m29w640ft m29w640fb 64 mbit (8mb x8 or 4mb x16, page, boot block) 3v supply flash memory feature summary supply voltage ?v cc = 2.7v to 3.6v for program, erase, read ?v pp =12 v for fast program (optional) asynchronous random/page read ? page width: 4 words ? page access: 25ns ? random access: 60ns, 70ns programming time ? 10s per byte/word typical ? 4 words / 8 bytes program 135 memory blocks ? 1 boot block and 7 parameter blocks, 8 kbytes each (top or bottom location) ? 127 main blocks, 64 kbytes each program/erase controller ? embedded byte/word program algorithms program/erase suspend and resume ? read from any block during program suspend ? read and program another block during erase suspend unlock bypass program command ? faster production/batch programming v pp /wp pin for fast program and write protect temporary block unprotection mode common flash interface ? 64-bit security code extended memory block extra block used as security block or to store additional information low power consumption ? standby and automatic standby 100,000 program/erase cycles per block electronic signature ? manufacturer code: 0020h ecopack ? packages fbga tsop48 (n) 12 x 20mm tfbga48 (za) 6x8mm table 1. device codes root part number device code m29w640ft 22edh m29w640fb 22fdh www.numonyx.com
contents m29w640ft, m29w640fb 2/71 contents 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 address inputs (a0-a21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 data inputs/outputs (dq0-dq7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 data inputs/outputs (dq8-dq14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 data input/output or address input (dq15a?1) . . . . . . . . . . . . . . . . . . . 11 2.5 chip enable (e ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.6 output enable (g ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.7 write enable (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.8 v pp /write protect (v pp/ wp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.9 reset/block temporary unprotect (rp ) . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.10 ready/busy output (rb ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.11 byte/word organization select (byte ) . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.12 v cc supply voltage (2.7v to 3.6v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.13 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3 output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.4 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 automatic standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6 special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6.1 electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6.2 block protect and chip unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 standard commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.1 read/reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.2 auto select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.3 read cfi query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
m29w640ft, m29w640fb contents 3/71 4.1.4 chip erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1.5 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1.6 erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.1.7 erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1.8 program suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1.9 program resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1.10 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.2 fast program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.1 double byte program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.2 quadruple byte program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.2.3 octuple byte program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2.4 double word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2.5 quadruple word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2.6 unlock bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2.7 unlock bypass program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2.8 unlock bypass reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3 block protection commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3.1 enter extended block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3.2 exit extended block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.3.3 block protect and chip unprotect commands . . . . . . . . . . . . . . . . . . . . 26 5 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1 data polling bit (dq7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2 toggle bit (dq6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3 error bit (dq5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.4 erase timer bit (dq3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.5 alternative toggle bit (dq2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 appendix a block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
contents m29w640ft, m29w640fb 4/71 appendix b common flash interface (c fi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 appendix c extended memory block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 c.1 factory locked extended block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 c.2 customer lockable extended block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 appendix d block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 d.1 programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 d.2 in-system technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
m29w640ft, m29w640fb list of tables 5/71 list of tables table 1. device codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. hardware protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. bus operations, byte = v il . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. bus operations, byte = v ih . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 6. commands, 16-bit mode, byte = v ih . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 7. commands, 8-bit mode, byte = v il. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 8. program, erase times and prog ram, erase endurance cycles. . . . . . . . . . . . . . . . . . . . . . 29 table 9. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 10. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 11. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 12. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 13. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 14. read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 15. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 16. write ac characteristics, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 17. reset/block temporary unprotect ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 18. tsop48 ? 48 lead plastic thin small outline, 12 x 20mm, package mechanical data . . . 44 table 19. tfbga48 6x8mm - 6x8 active ball array, 0.8mm pitch, package mechanical data . . . . . . 45 table 20. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 21. top boot block addresses, m29w640ft . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 22. bottom boot block addresses, m29w640fb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 23. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 24. cfi query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 25. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 26. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 27. primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 28. security code area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 29. extended block address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 30. programmer technique bus operations, byte = v ih or v il . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 31. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
list of figures m29w640ft, m29w640fb 6/71 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. tsop connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. tfbga48 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. data polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 5. data toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 6. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 figure 7. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 8. read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 9. page read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 10. write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 11. write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 12. reset/block temporary unprotect ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 13. accelerated program timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 14. tsop48 ? 48 lead plastic thin small outline, 12 x 20mm, top view package outline . . . . 44 figure 15. tfbga48 6x8mm - 6x8 active ball array, 0.8mm pitch, package outline . . . . . . . . . . . . . . 45 figure 16. programmer equipment group protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 17. programmer equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 18. in-system equipment group protect flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 19. in-system equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
m29w640ft, m29w640fb summary description 7/71 1 summary description the m29w640f is a 64 mbit (8mb x8 or 4mb x16) non-volatile memory that can be read, erased and reprogrammed. these operations can be performed using a single low voltage (2.7 to 3.6v) supply. on power-up the memory defaults to its read mode. the memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. blocks can be protected in units of 256 kbyte (generally groups of four 64 kbyte blocks ), to prevent accidental program or erase commands from modifying the memory. program and erase commands are written to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified. the command set required to control the memory is consistent with jedec standards. the device features an asymmetrical blocked architecture. the device has an array of 135 blocks: 8 parameters blocks of 8 kbytes each (or 4 kwords each) 127 main blocks of 64 kbytes each (or 32 kwords each) m29w640ft has the parameter blocks at the top of the memory address space while the m29w640fb locates the parameter blocks starting from the bottom. the m29w640f has an extra block, the extended block, of 128 words in x16 mode or of 256 byte in x8 mode that can be accessed using a dedicated command. the extended block can be protected and so is useful for storing security information. however the protection is not reversible, once protected the protection cannot be undone. chip enable, output enable and write enable signals control the bus operation of the memory. they allow simple connection to most microprocessors, often without additional logic. the v pp /wp signal is used to enable faster programming of the device, enabling multiple word/byte programming. if this signal is held at v ss , the boot block, and its adjacent parameter block, are protected from program and erase operations. the device supports asynchronous random read and page read from all blocks of the memory array. the memories are offered in tsop48 (12x 20mm) and tfbga48 (6x8mm, 0.8mm pitch) packages. in order to meet environmental requirements, st offers the m29w640ft and the m29w640fb in ecopack ? packages. ecopack packages are lead-free. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. the memory is delivered with all the bits erased (set to 1).
summary description m29w640ft, m29w640fb 8/71 figure 1. logic diagram table 2. signal names a0-a21 address inputs dq0-dq7 data inputs/outputs dq8-dq14 data inputs/outputs dq15a?1 (or dq15) data inpu t/output or address input (or data input/output) e chip enable g output enable w write enable rp reset/block temporary unprotect rb ready/busy output byte byte/word organization select v cc supply voltage v pp /wp supply voltage for fast program (optional) or write protect v ss ground nc not connected internally ai11250 22 a0-a21 w dq0-dq14 v cc m29w640ft m29w640fb e v ss 15 g rp dq15a?1 byte rb v pp /wp
m29w640ft, m29w640fb summary description 9/71 figure 2. tsop connections dq3 dq9 dq2 a6 dq0 w a3 rb dq6 a8 a9 dq13 a17 a10 dq14 a2 dq12 dq10 dq15a?1 v cc dq4 dq5 a7 dq7 v pp /wp a21 m29w640ft m29w640fb 12 1 13 24 25 36 37 48 dq8 a20 a19 a1 a18 a4 a5 dq1 dq11 g a12 a13 a16 a11 byte a15 a14 v ss e a0 rp v ss ai11251
summary description m29w640ft, m29w640fb 10/71 figure 3. tfbga48 connections (top view through package) 6 5 4 3 2 1 v ss a15 a14 a12 a13 dq3 dq11 dq10 a18 v pp / wp rb dq1 dq9 dq8 dq0 a6 a17 a7 g e a0 a4 a3 dq2 dq6 dq13 dq14 a10 a8 a9 dq4 v cc dq12 dq5 a19 a21 rp w a11 dq7 a1 a2 v ss a5 a20 a16 byte c b a e d f g h dq15 a?1 ai11554
m29w640ft, m29w640fb signal descriptions 11/71 2 signal descriptions see figure 1: logic diagram , and table 2: signal names , for a brief overview of the signals connected to this device. 2.1 address inputs (a0-a21) the address inputs select the cells in the memory array to access during bus read operations. during bus write operations they control the commands sent to the command interface of the program/erase controller. 2.2 data inputs/outputs (dq0-dq7) the data i/o outputs the data stored at the selected address during a bus read operation. during bus write operations they represent the commands sent to the command interface of the program/erase controller. 2.3 data inputs/outputs (dq8-dq14) the data i/o outputs the data stored at the selected address during a bus read operation when byte is high, v ih . when byte is low, v il , these pins are not used and are high impedance. during bus write operations the command register does not use these bits. when reading the status register these bits should be ignored. 2.4 data input/output or address input (dq15a?1) when byte is high, v ih , this pin behaves as a data input/output pin (as dq8-dq14). when byte is low, v il , this pin behaves as an address pin; dq15a?1 low will select the lsb of the addressed word, dq15a?1 high will select the msb. throughout the text consider references to the data input/output to include this pin when byte is high and references to the address inputs to include this pin when byte is low except when stated explicitly otherwise. 2.5 chip enable (e ) the chip enable, e , activates the memory, allowing bus read and bus write operations to be performed. when chip enable is high, v ih , all other pins are ignored. 2.6 output enable (g ) the output enable, g , controls the bus read operation of the memory.
signal descriptions m29w640ft, m29w640fb 12/71 2.7 write enable (w ) the write enable, w , controls the bus write operation of the memory?s command interface. 2.8 v pp /write protect (v pp /wp ) the v pp /write protect pin provides two functions. the v pp function allows the memory to use an external high voltage power supply to reduce the time required for unlock bypass program operations. the write protect function provides a hardware method of protecting the two outermost boot blocks. the v pp /write protect pin must not be left floating or unconnected. when v pp /write protect is low, v il , the memory protects the two outermost boot blocks; program and erase operations in this block are ignored while v pp /write protect is low, even when rp is at v id . when v pp /write protect is high, v ih , the memory reverts to the previous protection status of the two outermost boot blocks. program and erase operations can now modify the data in the two outermost boot blocks unless the block is protected using block protection. applying v pph to the v pp /wp pin will temporarily unprotect an y block previously protected (including the two outermost parameter blocks) using a high voltage block protection technique (in-system or programmer technique). see table 3: hardware protection for details. when v pp /write protect is raised to v pp the memory automatically enters the unlock bypass mode. when v pp /write protect returns to v ih or v il normal operation resumes. during unlock bypass program operations the memory draws i pp from the pin to supply the programming circuits. see the description of the unlock bypass command in the command interface section. the transitions from v ih to v pp and from v pp to v ih must be slower than t vhvpp , see figure 13: accelerated program timing waveforms . never raise v pp /write protect to v pp from any mode except read mode, otherwise the memory may be left in an indeterminate state. a 0.1f capacitor should be connected between the v pp /write protect pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during unlock bypass program, i pp . table 3. hardware protection v pp /wp rp function v il v ih 2 outermost parameter blocks protec ted from program/erase operations v id all blocks temporarily unprotected except the 2 outermost blocks v ih or v id v id all blocks temporarily unprotected v pph v ih or v id all blocks temporarily unprotected
m29w640ft, m29w640fb signal descriptions 13/71 2.9 reset/block temporary unprotect (rp ) the reset/block temporary unprotect pin can be used to apply a hardware reset to the memory or to temporarily unprotect al l blocks that have been protected. note that if v pp /wp is at v il , then the two outermost boot bl ocks will remain protected even if rp is at v id . a hardware reset is achieved by holding reset/block temporary unprotect low, v il , for at least t plpx . after reset/block temporary unprotect goes high, v ih , the memory will be ready for bus read and bus write operations after t phel or t rhel , whichever occurs last. see the ready/busy output section, table 17: reset/block temporary unprotect ac characteristics and figure 12: reset/block temporary unprotect ac waveforms , for more details. holding rp at v id will temporarily unprotect the protec ted blocks in the memory. program and erase operations on all blocks will be possible. the transition from v ih to v id must be slower than t phphh . 2.10 ready/busy output (rb ) the ready/busy pin is an open-drain output that can be used to identify when the device is performing a program or erase operation. during program or erase operations ready/busy is low, v ol . ready/busy is high-impedance during read mode, auto select mode and erase suspend mode. after a hardware reset, bus read and bus write operations cannot begin until ready/busy becomes high-impedance. see table 17: reset/block temporary unprotect ac characteristics and figure 12: reset/block temporary unprotect ac waveforms , for more details. the use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. a low will then indicate that one, or more, of the memories is busy. 2.11 byte/word organization select (byte ) the byte/word organization select pin is used to switch between the x8 and x16 bus modes of the memory. when byte/word organization select is low, v il , the memory is in x8 mode, when it is high, v ih , the memory is in x16 mode.
signal descriptions m29w640ft, m29w640fb 14/71 2.12 v cc supply voltage (2.7v to 3.6v) v cc provides the power supply for all operations (read, program and erase). the command interface is disabled when the v cc supply voltage is less than the lockout voltage, v lko . this prevents bus write operations from accidentally damaging the data during power up, power down and power surges. if the program/erase controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. a 0.1f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations, i cc3 . 2.13 v ss ground v ss is the reference for all voltage measurements. the device features two v ss pins which must be both connected to the system ground.
m29w640ft, m29w640fb bus operations 15/71 3 bus operations there are five standard bus operations that control the device. these are bus read, bus write, output disable, standby and automatic standby. see table 4: bus operations, byte = v il and table 5: bus operations, byte = v ih , for a summary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus operations. 3.1 bus read bus read operations read from the memory cells, or specific registers in the command interface. a valid bus read operation involves setting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable high, v ih . the data inputs /outputs will output the value, see figure 8: read mode ac waveforms , and table 14: read ac characteristics , for details of when the output becomes valid. 3.2 bus write bus write operations write to the command interface. to speed up the read operation the memory array can be read in page mode where data is internally read and stored in a page buffer. the page has a size of 4 words and is addressed by the address inputs a0-a1. a valid bus write operation begins by setting the desired address on the address inputs. the address inputs are latched by the comman d interface on the falling edge of chip enable or write enable, whichever occurs last. the data inputs/outputs are latched by the command interface on the rising edge of chip enable or write enable, whichever occurs first. output enable must remain high, v ih , during the whole bus write operation. see figure 10: write ac waveforms, write enable controlled , figure 11: write ac waveforms, chip enable controlled , and table 15: write ac characterist ics, write enable controlled and table 16: write ac characteristics, chip enable controlled , for details of the timing requirements. 3.3 output disable the data inputs/outputs are in the high impedance state when output enable is high, v ih . 3.4 standby when chip enable is high, v ih , the memory enters standby mode and the data inputs/outputs pins are placed in the high-impedance state. to reduce the supply current to the standby supply current, i cc2 , chip enable should be held within v cc 0.2v. for the standby current level see table 13: dc characteristics . during program or erase oper ations the memory will contin ue to use the program/erase supply current, i cc3 , for program or erase operations until the operation completes.
bus operations m29w640ft, m29w640fb 16/71 3.5 automatic standby if cmos levels (v cc 0.2v) are used to drive the bus and the bus is inactive for 300ns or more the memory enters automatic standby where the internal supply current is reduced to the standby supply current, i cc2 . the data inputs/outputs will still output data if a bus read operation is in progress. 3.6 special bus operations additional bus operations can be performed to read the electronic signature and also to apply and remove block protection. these bus operations are intended for use by programming equipment and are not usually used in applications. they require v id to be applied to some pins. 3.6.1 electronic signature the memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. these codes can be read by applying the signals listed in ta b l e 4 : bus operations, byte = v il and table 5: bus operations, byte = v ih . 3.6.2 block protect and chip unprotect groups of blocks can be protected against accidental program or erase. the protection groups are shown in appendix a: block addresses ta b l e 2 1 and ta bl e 2 2 . the whole chip can be unprotected to allow the data inside the blocks to be changed. the v pp /write protect pin can be used to protect the two outermost boot blocks. when v pp /write protect is at v il the two outermost boot blocks are protected and remain protected regardless of the block protection status or the reset/block temporary unprotect pin status. block protect and chip unprotect operations are described in appendix d: block protection .
m29w640ft, m29w640fb bus operations 17/71 table 4. bus operations, byte = v il (1) operation e g w address inputs dq15a?1, a0-a21 data inputs/outputs dq14-dq8 dq7-dq0 bus read v il v il v ih cell address hi-z data output bus write v il v ih v il command address hi-z data input output disable x v ih v ih x hi-z hi-z standby v ih x x x hi-z hi-z read manufacturer code v il v il v ih a0-a3 = v il , a6 = v il , a9 = v id , others v il or v ih hi-z 20h read device code v il v il v ih a0 = v ih , a1-a3= v il , a6 = v il , a9 = v id , others v il or v ih hi-z edh (m29w640ft) fdh (m29w640fb) read extended memory block verify code v il v il v ih a0 -a1 = v ih , a2-a3= v il , a6 = v il , a9 = v id , others v il or v ih hi-z 80h (factory locked) 00h (customer lockable) read block protection status v il v il v ih a0,a2,a3, a6= v il , a1= v ih , a9 = v id , a12-a21 = block address, others v il or v ih hi-z 01h (protected) 00h (unprotected) 1. x = v il or v ih . table 5. bus operations, byte = v ih (1) operation e g w address inputs a0-a21 data inputs/outputs dq15a?1, dq14-dq0 bus read v il v il v ih cell address data output bus write v il v ih v il command address data input output disable x v ih v ih xhi-z standby v ih xxx hi-z read manufacturer code v il v il v ih a0-a3 = v il , a6 = v il , a9 = v id , others v il or v ih 0020h read device code v il v il v ih a0 = v ih , a1-a3= v il , a6 = v il , a9 = v id , others v il or v ih 22edh (m29w640ft) 22fdh (m29w640fb) read extended memory block verify code v il v il v ih a0 -a1 = v ih , a2-a3= v il , a6 = v il , a9 = v id , others v il or v ih 80h (factory locked) 00h (customer lockable) read block protection status v il v il v ih a0,a2,a3, a6= v il , a1 = v ih , a9 = v id , a12-a21 = block address, others v il or v ih 0001h (protected) 0000h (unprotected) 1. x = v il or v ih .
command interface m29w640ft, m29w640fb 18/71 4 command interface all bus write operations to the memory are interpreted by the command interface. commands consist of one or more sequential bus write operations. failure to observe a valid sequence of bus write operations will resu lt in the memory retu rning to read mode. the long command sequences are imposed to maximize data security. the address used for the commands changes depending on whether the memory is in 16- bit or 8-bit mode. see either ta bl e 6 , or ta b l e 7 , depending on the configuration that is being used, for a summary of the commands. 4.1 standard commands 4.1.1 read/reset command the read/reset command returns the memory to its read mode. it also resets the errors in the status register. either one or three bus write operations can be used to issue the read/reset command. the read/reset command can be issued, between bus write cycles before the start of a program or erase operation, to return the device to read mode. if the read/reset command is issued during the timeout of a block erase operation then the memory will take up to 10s to abort. during the abort period no valid data can be read from the memory. the read/reset command will not abort an erase operation when issued while in erase suspend. 4.1.2 auto select command the auto select command is used to read the manufacturer code, the device code, the block protection status and the extended me mory block verify code. three consecutive bus write operations are required to issue the auto select command. once the auto select command is issued the memory remains in auto select mode until a read/reset command is issued. read cfi query and read/reset commands are accepted in auto select mode, all other commands are ignored. in auto select mode, the manufacturer code and the device code can be read by using a bus read operation with addresses and control signals set as shown in ta b l e 4 : b u s operations, byte = v il and table 5: bus operations, byte = v ih , except for a9 that is ?don?t care?. the block protection status of each block can be read using a bus read operation with addresses and control si gnals set as shown in table 4: bus operations, byte = v il and table 5: bus operations, byte = v ih , except for a9 that is ?don?t care?. if the addressed block is protected then 01h is output on data inputs/outputs dq0-dq7, otherwise 00h is output (in 8-bit mode). the protection status of the extended memory block, or extended memory block verify code, can be read using a bus read operation with addresses and control signals set as shown in table 4: bus operations, byte = v il and table 5: bus operations, byte = v ih , except for a9 that is ?don?t care?. if the extended block is "factory locked" then 80h is output on data input/outputs dq0-dq7, otherwise 00h is output (8-bit mode).
m29w640ft, m29w640fb command interface 19/71 4.1.3 read cfi query command the read cfi query command is used to read data from the common flash interface (cfi) memory area. this command is valid when the device is in the read array mode, or when the device is in autoselected mode. one bus write cycle is required to issue the read cfi query command. once the command is issued subsequent bus read operations read from the common flash interface memory area. the read/reset command must be issued to return the device to the previous mode (the read array mode or autoselected mode). a second read/reset command would be needed if the device is to be put in the read array mode from autoselected mode. see appendix b: common flash interface (cfi) , tables 23 , 24 , 25 , 26 , 27 and 28 for details on the information contained in the common flash interface (cfi) memory area. 4.1.4 chip erase command the chip erase command can be used to erase the entire chip. six bus write operations are required to issue the chip erase command and start the program/erase controller. if any blocks are protected then these are ignored and all the other blocks are erased. if all of the blocks are protected the chip erase operation appears to start but will terminate within about 100s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during the erase operation the memory will ignore all commands, including the erase suspend command. it is not possible to issue any command to abort the operation. typical chip erase times are given in table 8: program, erase times and program, erase endurance cycles . all bus read operations during the chip erase operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the chip erase operation has complet ed the memory will return to the read mode, unless an error has occurred. when an error oc curs the memory will co ntinue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. the chip erase command sets all of the bits in unprotected blocks of the memory to ?1?. all previous data is lost.
command interface m29w640ft, m29w640fb 20/71 4.1.5 block erase command the block erase command can be used to erase a list of one or more blocks. six bus write operations are required to select the first block in the list. each additional block in the list can be selected by repeating the sixth bus write operation using the address of the additional block. the block erase operation starts the program/erase controller about 50s after the last bus write operation. once the program/erase controller starts it is not possible to select any more blocks. each additional block must therefore be selected within 50s of the last block. the 50s timer restarts when an additional block is selected. the status register can be read after the sixth bus write operation. see the status register section for details on how to identify if the program/erase controller has started the block erase operation. if any selected blocks are protected then these are ignored and all the other selected blocks are erased. if all of the selected blocks are protected the block erase operation appears to start but will terminate wit hin about 100s, leaving the data un changed. no erro r condition is given when protected blocks are ignored. during the block erase operat ion the memory will ignore a ll commands except the erase suspend command. typical block erase times are given in table 8: program, erase times and program, erase endurance cycles . all bus read operations during the block erase operation will output the status register on the data input s/outputs. see the section on the status register for more details. after the block erase operation has complete d the memory will return to the read mode, unless an error has occurred. when an error oc curs the memory will co ntinue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. the block erase command sets all of the bits in the unprotected selected blocks to ?1?. all previous data in the selected blocks is lost. 4.1.6 erase suspend command the erase suspend command may be used to temporarily suspend a block erase operation and return the memory to read mode. the command requires one bus write operation. the program/erase controller will suspend within the erase suspend latency time of the erase suspend command being issued. once the program/erase controller has stopped the memory will be set to re ad mode and the erase will be suspended. if the erase suspend command is issued during the period when the memory is waiting for an additional block (before the program/erase controller starts) then the erase is suspended immediately and will start immediately when t he erase resume command is i ssued. it is not possible to select any further blocks to erase after the erase resume. during erase suspend it is possible to read and program cells in blocks that are not being erased; both read and program operations behave as normal on these blocks. if any attempt is made to program in a protected block or in the suspended block then the program command is ignored and the data remains unchanged. the status register is not read and no error condition is given. reading from bloc ks that are being erased will output the status register. it is also possible to issue the auto select, read cfi query and unlock bypass commands during an erase suspend. the read/reset command must be issued to return the device to read array mode before the resume command will be accepted.
m29w640ft, m29w640fb command interface 21/71 4.1.7 erase resume command the erase resume command must be used to restart the program/erase controller after an erase suspend. the device must be in read array mode before the resume command will be accepted. an erase can be suspended and resumed more than once. 4.1.8 program suspend command the program suspend command allows the system to interrupt a program operation so that data can be read from any block. when the program suspend command is issued during a program operation, the device suspends the program operation within the program suspend latency time (see table 8: program, erase times and program, erase endurance cycles for value) and updates the status register bits. after the program operation has been suspended, the system can read array data from any address. however, data read from program-suspended addresses is not valid. the program suspend command may also be issued during a program operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the extended block area (one-time program area), the user must use the proper command sequences to enter and exit this region. the system may also issue the auto select command sequence when the device is in the program suspend mode. the system can read as many auto select codes as required. when the device exits the auto select mode, the device reverts to the program suspend mode, and is ready for another valid operation. see auto select command sequence for more information. 4.1.9 program resume command after the program resume command is issued, the device reverts to programming. the controller can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see write operation status for more information. the system must write the program resume command, to exit the program suspend mode and to continue the programming operation. further issuing of the resume command is ignored. another program suspend command can be written after the device has resumed programming.
command interface m29w640ft, m29w640fb 22/71 4.1.10 program command the program command can be used to program a value to one address in the memory array at a time. the command requires four bus write operations, the final write operation latches the address and data, and starts the program/erase controller. programming can be suspended and then resumed by issuing a program suspend command and a program resume command, respectively (see section 4.1.8: program suspend command and section 4.1.9: program resume command ). if the address falls in a protected block then the program command is ignored, the data remains unchanged. the status register is ne ver read and no error condition is given. during the program operation the memory will i gnore all commands. it is not possible to issue any command to abort or pause the operation. typical program times are given in table 8: program, erase times and program, erase endurance cycles . bus read operations during the program operation will output the status register on the data inputs/outputs. see the section on the status register for more details. after the program operat ion has completed the memory will re turn to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. note that the program command cannot change a bit set at ?0? back to ?1?. one of the erase commands must be used to set all the bits in a block or in the whole me mory from ?0? to ?1?.
m29w640ft, m29w640fb command interface 23/71 4.2 fast program commands there are four fast program commands available to improve the programming throughput, by writing several adjacent words or bytes in parallel. the double, quadruple and octuple byte program commands are available for x8 operations, while the double quadruple word program command are available for x16 operations. fast program commands can be suspended and then resumed by issuing a program suspend command and a program resume command, respectively (see section 4.1.8: program suspend command and section 4.1.9: program resume command ). when v pph is applied to the v pp /write protect pin the memory automatically enters the fast program mode. the user can then choose to issue any of the fast program commands. care must be taken because applying a v pph to the v pp /wp pin will temporarily unprotect any protected block. 4.2.1 double byte program command the double byte program command is used to write a page of two adjacent bytes in parallel. the two bytes must differ only in dq15a-1. three bus write cycles are necessary to issue the double byte program command. 1. the first bus cycle sets up th e double byte program command. 2. the second bus cycle latches the address and the data of the first byte to be written. 3. the third bus cycle latches the address and the data of the second byte to be written. 4.2.2 quadruple byte program command the quadruple byte program command is used to write a page of four adjacent bytes in parallel. the four bytes must differ only for addresses a0, dq15a-1. five bus write cycles are necessary to issue the quadruple byte program command. 1. the first bus cycle sets up the quadruple byte program command. 2. the second bus cycle latches the address and the data of the first byte to be written. 3. the third bus cycle latches the address and the data of the second byte to be written. 4. the fourth bus cycle latches the address and the data of the third byte to be written. 5. the fifth bus cycle latches the address and the data of the fourth byte to be written and starts the program/erase controller.
command interface m29w640ft, m29w640fb 24/71 4.2.3 octuple byte program command this is used to write eight adjacent bytes, in x8 mode, simultaneously. the addresses of the eight bytes must differ only in a1, a0 and dq15a-1. nine bus write cycles are necessary to issue the command: 1. the first bus cycle sets up the command. 2. the second bus cycle latches the address and the data of the first byte to be written. 3. the third bus cycle latches the address and the data of the second byte to be written. 4. the fourth bus cycle latches the address and the data of the third byte to be written. 5. the fifth bus cycle latches the address and the data of the fourth byte to be written. 6. the sixth bus cycle latches the address and the data of the fifth byte to be written. 7. the seventh bus cycle latches the address and the data of the sixth byte to be written. 8. the eighth bus cycle latches the address and the data of the seventh byte to be written. 9. the ninth bus cycle latches the address and the data of the eighth byte to be written and starts the program/erase controller. 4.2.4 double word program command the double word program command is used to write a page of two adjacent words in parallel. the two words must differ only for the address a0. three bus write cycles are necessary to issue the double word program command. the first bus cycle sets up the quadruple word program command. the second bus cycle latches the address and the data of the first word to be written. the third bus cycle latches the address and the data of the second word to be written and starts the program/erase controller. after the program operat ion has completed the memory will re turn to the read mode, unless an error has occurred. when an error occurs bus read opera tions will continue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. note that the fast program commands cannot change a bit set at ?0? back to ?1?. one of the erase commands must be used to set all the bits in a block or in the whole memory from ?0? to ?1?. typical program times are given in table 8: program, erase times and program, erase endurance cycles .
m29w640ft, m29w640fb command interface 25/71 4.2.5 quadruple word program command this is used to write a page of four adjacent words (or 8 adjacent bytes), in x16 mode, simultaneously. the addresses of the four words must differ only in a1 and a0. five bus write cycles are necessary to issue the command: the first bus cycle sets up the command. the second bus cycle latches the address and the data of the first word to be written. the third bus cycle latches the address and the data of the second word to be written. the fourth bus cycle latches the address and the data of the third word to be written. the fifth bus cycle latches the address and the data of the fourth word to be written and starts the program/erase controller. 4.2.6 unlock bypass command the unlock bypass command is used in conjunction with the unlock bypass program command to program the memory faster than with the standard program commands. when the cycle time to the device is long, considerab le time saving can be made by using these commands. three bus write operations are required to issue the unlock bypass command. once the unlock bypass command has been is sued the memory will only accept the unlock bypass program command and the unlock bypass reset command. the memory can be read as if in read mode. when v pp is applied to the v pp /write protect pin the memory automatically enters the unlock bypass mode and the unlock bypass program command can be issued immediately. 4.2.7 unlock bypass program command the unlock bypass command is used in conjunction with the unlock bypass program command to program the memory. when the cycle time to the device is long, considerable time saving can be made by using these commands. three bus write operations are required to issue the unlock bypass command. once the unlock bypass command has been is sued the memory will only accept the unlock bypass program command and the unlock bypass reset command. the memory can be read as if in read mode. the memory offers accelerated program operations through the v pp /write protect pin. when the system asserts v pp on the v pp /write protect pin, the memory automatically enters the unlock bypass mo de. the system may then write the two-cycle unlock bypass program command sequence. the memory uses the higher voltage on the v pp /write protect pin, to accelerate the unlock bypass program operation. never raise v pp /write protect to v pp from any mode except read mode, otherwise the memory may be left in an indeterminate state. 4.2.8 unlock b ypass reset command the unlock bypass reset command can be used to return to read/reset mode from unlock bypass mode. two bus write operations are required to issue the unlock bypass reset command. read/reset command does not exit from unlock bypass mode.
command interface m29w640ft, m29w640fb 26/71 4.3 block protection commands 4.3.1 enter extended block command the device has an extra 256 byte block (extended block) that can only be accessed using the enter extended block command. three bu s write cycles are required to issue the extended block command. once the command has been issued the device enters extended block mode where all bus read or write operations to the boot block addresses access the extended block. the extended block (with the same address as the boot blocks) cannot be erased, and can be treated as one-time programmable (otp) memory. in extended block mode the boot blocks are not accessible. to exit from the extended block mode the exit extended block command must be issued. the extended block can be protected, however once protected the protection cannot be undone. 4.3.2 exit extended block command the exit extended block command is used to exit from the extended block mode and return the device to read mode. four bus write operations are required to issue the command. 4.3.3 block protect and chip unprotect commands groups of blocks can be protected against accidental program or erase. the protection groups are shown in appendix a: block addresses , table 21: top boot block addresses, m29w640ft and table 22: bottom boot block addresses, m29w640fb . the whole chip can be unprotected to allow the data inside the blocks to be changed. block protect and chip unprotect operations are described in appendix d: block protection .
m29w640ft, m29w640fb command interface 27/71 table 6. commands, 16-bit mode, byte = v ih (1) command length bus write operations 1st 2nd 3rd 4th 5th 6th addr data addr data addr data addr data addr data addr data read/reset 1x f0 3 555 aa 2aa 55 x f0 auto select 3 555 aa 2aa 55 555 90 program 4 555 aa 2aa 55 555 a0 pa pd double word program 3 555 50 pa0 pd0 pa1 pd1 quadruple word program 5 5 5 5 5 6 pa 0 p d 0 pa 1 p d 1 pa 2 p d 2 pa 3 p d 3 unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program 2 x a0 pa pd unlock bypass reset 2 x 90 x 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 block erase 6+ 555 aa 2aa 55 555 80 555 aa 2aa 55 ba 30 program/erase suspend 1x b0 program/erase resume 1x 30 read cfi query 1 55 98 enter extended block 3 555 aa 2aa 55 555 88 exit extended block 4 555 aa 2aa 55 555 90 x 00 1. x don?t care, pa program address, pd program data, ba an y address in the block. all values in the table are in hexadecimal. the command interface only uses a?1, a0-a10 and dq0-dq7 to verify the commands; a11-a20, dq8- dq14 and dq15 are don?t care. dq15a?1 is a?1 when byte is v il or dq15 when byte is v ih .
command interface m29w640ft, m29w640fb 28/71 table 7. commands, 8-bit mode, byte = v il command length bus write operations (1) 1st 2nd 3rd 4th 5th 6th 7th 8th 9th add data add data add data add data add data add data add data add data add data read/reset 1x f0 3 aaa aa 555 55 x f0 auto select 3 aaa aa 555 55 aaa 90 program 4 aaa aa 555 55 aaa a0 pa pd double byte program 3 aaa 50 pa0 pd0 pa1 pd1 quadruple byte program 5 aaa 56 pa0 pd0 pa1 pd1 pa2 pd2 pa3 pd3 octuple byte program 9 a a a 8 b pa 0 p d 0 pa 1 p d 1 pa 2 p d 2 pa 3 p d 3 pa 4 p d 4 pa 5 p d 5 pa 6 p d 6 pa 7 p d 7 unlock bypass 3 aaa aa 555 55 aaa 20 unlock bypass program 2xa0papd unlock bypass reset 2x 90x00 chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 block erase 6+ aaa aa 555 55 aaa 80 aaa aa 555 55 ba 30 program/erase suspend 1xb0 program/erase resume 1x 30 read cfi query 1aa 98 enter extended block 3 aaa aa 555 55 aaa 88 exit extended block 4 aaa aa 555 55 aaa 90 x 00 1. x don?t care, pa program address, pd program data, ba an y address in the block. all values in the table are in hexadecimal. the command interface only uses a?1, a0-a10 and dq0-dq7 to verify the commands; a11-a20, dq8- dq14 and dq15 are don?t care. dq15a?1 is a?1 when byte is v il or dq15 when byte is v ih .
m29w640ft, m29w640fb command interface 29/71 table 8. program, erase times and program, erase endurance cycles parameter min typ (1)(2) max (2) unit chip erase 80 400 (3) s block erase (64 kbytes) 0.8 6 (4) s erase suspend latency time 50 (4) s program (byte or word) 10 200 (3) s double byte 10 200 (3) s double word /quadruple byte program 10 200 (3) s quadruple word / octuple byte program 10 200 (3) s chip program (byte by byte) 80 400 (3) s chip program (word by word) 40 200 (3) s chip program (double word/quadruple byte program) 20 100 (3) s chip program (quadruple word/octuple byte program) 10 50 (3) s program suspend latency time 4 s program/erase cycles (per block) 100,000 cycles data retention 20 years 1. typical values measured at room temperature and nominal voltages. 2. sampled, but not 100% tested. 3. maximum value measured at worst case conditions for both temperature and v cc after 100,00 program/erase cycles. 4. maximum value measured at worst case conditions for both temperature and v cc .
status register m29w640ft, m29w640fb 30/71 5 status register bus read operations from any address always read the status register during program and erase operations. it is also read during erase suspend when an address within a block being erased is accessed. the bits in the status register are summarized in table 9: status register bits . 5.1 data polling bit (dq7) the data polling bit can be used to identi fy whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. the data polling bit is output on dq7 when the status register is read. during program operations the data polling bi t outputs the compleme nt of the bit being programmed to dq7. after successful completion of the program operation the memory returns to read mode and bus read operations from the address just programmed output dq7, not its complement. during erase operations the data polling bit outp uts ?0?, the complement of the erased state of dq7. after successful completion of the erase operation the memory returns to read mode. in erase suspend mode the da ta polling bit will output a ?1? during a bus read operation within a block being erased. the data polling bit will change from a ?0? to a ?1? when the program/erase controller has suspended the erase operation. figure 4: data polling flowchart , gives an example of how to use the data polling bit. a valid address is the address being programmed or an address within the block being erased. 5.2 toggle bit (dq6) the toggle bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has responded to an erase suspend. the toggle bit is output on dq6 when the status register is read. during program and erase operations the toggle bit changes from ?0? to ?1? to ?0?, etc., with successive bus read operations at any addres s. after successful completion of the operation the memory returns to read mode. during erase suspend mo de the toggle bit will output when addressing a cell within a block being erased. the toggle bit will stop togglin g when the program/erase controller has suspended the erase operation. figure 5: data toggle flowchart , gives an example of how to use the data toggle bit.
m29w640ft, m29w640fb status register 31/71 5.3 error bit (dq5) the error bit can be used to identify errors detected by the program/erase controller. the error bit is set to ?1? when a program, block erase or chip erase operation fails to write the correct data to the memory. if the error bit is set a read/reset command must be issued before other commands are issued. the error bit is output on dq5 when the status register is read. note that the program command cannot change a bit set to ?0? back to ?1? and attempting to do so will set dq5 to ?1?. a bus read operation to that address will show the bit is still ?0?. one of the erase commands must be used to set all the bits in a block or in the whole memory from ?0? to ?1?. 5.4 erase timer bit (dq3) the erase timer bit can be used to identify the start of program/erase controller operation during a block erase command. once the program/erase controller starts erasing the erase timer bit is set to ?1?. before the program/erase controller starts the erase timer bit is set to ?0? and additional blocks to be eras ed may be written to the command interface. the erase timer bit is output on dq3 when the status register is read. 5.5 alternative toggle bit (dq2) the alternative toggle bit can be used to monitor the program/erase controller during erase operations. the alternative toggle bit is output on dq2 when the status register is read. during chip erase and block erase operations the toggle bit changes from ?0? to ?1? to ?0?, etc., with successive bus read operations from addresses within the blocks being erased. a protected block is treated the same as a block not being erased. once the operation completes the memory returns to read mode. during erase suspend the alternative toggle bi t changes from ?0? to ?1? to ?0?, etc. with successive bus read operations from addresses within the blocks being erased. bus read operations to addresses within blocks not be ing erased will output the me mory cell data as if in read mode. after an erase operation that causes the error bit to be set the alternative toggle bit can be used to identify which block or blocks have caused the error. the alternative toggle bit changes from ?0? to ?1? to ?0 ?, etc. with successive bus read operations from addresses within blocks that have not erased correctly. the alternative toggle bit does not change if the addressed block has erased correctly.
status register m29w640ft, m29w640fb 32/71 figure 4. data polling flowchart table 9. status register bits (1) 1. unspecified data bits should be ignored. operation address dq7 dq6 dq5 dq3 dq2 rb program any address dq7 toggle 0 ? ? 0 program during erase suspend any address dq7 toggle 0 ? ? 0 program error any address dq7 toggle 1 ? ? hi-z chip erase any address 0 toggle 0 1 toggle 0 block erase before timeout erasing block 0 toggle 0 0 toggle 0 non-erasing block 0 toggle 0 0 no toggle 0 block erase erasing block 0 toggle 0 1 toggle 0 non-erasing block 0 toggle 0 1 no toggle 0 erase suspend erasing block 1 no toggle 0 ? toggle hi-z non-erasing block data read as normal hi-z erase error good block address 0 toggle 1 1 no toggle hi-z faulty block address 0 toggle 1 1 toggle hi-z read dq5 & dq7 at valid address start read dq7 at valid address fail pass ai90194 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no
m29w640ft, m29w640fb status register 33/71 figure 5. data toggle flowchart read dq6 start read dq6 twice fail pass ai90195b dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle read dq5 & dq6
maximum rating m29w640ft, m29w640fb 34/71 6 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device relia bility. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. refer also to the stmicroelectronics sure program and other relevant quality documents. table 10. absolute maximum ratings symbol parameter min max unit t bias temperature under bias ?50 125 c t stg storage temperature ?65 150 c v io input or output voltage (1)(2) 1. minimum voltage may undershoot to ?2v during trans ition and for less than 20ns during transitions. 2. maximum voltage may overshoot to v cc +2v during transition and for less than 20ns during transitions. ?0.6 v cc +0.6 v v cc supply voltage ?0.6 4 v v id identification voltage ?0.6 13.5 v v pp (3) 3. v pp must not remain at 12v for more than a total of 80hrs. program voltage ?0.6 13.5 v
m29w640ft, m29w640fb dc and ac parameters 35/71 7 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristic tables that follow are derived from tests performed under the measurement conditions summarized in the relevant tables. designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. figure 6. ac measurement i/o waveform figure 7. ac measurement load circuit table 11. operating and ac measurement conditions parameter m29w640ft, m29w640fb unit min max v cc supply voltage 2.7 3.6 v ambient operating temperature ?40 85 c load capacitance (c l )30pf input rise and fall times 10 ns input pulse voltages 0 to v cc v input and output timing ref. voltages v cc /2 v ai05557 v cc 0v v cc /2 ai05558 c l c l includes jig capacitance device under test 25k v cc 25k v cc 0.1f v pp 0.1f
dc and ac parameters m29w640ft, m29w640fb 36/71 1. sampled only, not 100% tested. table 12. device capacitance symbol parameter test condition min max unit c in input capacitance v in = 0v 6 pf c out output capacitance v out = 0v 12 pf table 13. dc characteristics symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 supply current (read) e = v il , g = v ih , f = 6mhz 10 ma i cc2 supply current (standby) e = v cc 0.2v, rp = v cc 0.2v 100 a i cc3 supply current (program/erase) program/erase controller active v pp /wp = v il or v ih 20 ma v pp /wp = v pp 20 ma v il input low voltage ?0.5 0.8 v v ih input high voltage 0.7v cc v cc +0.3 v v pp voltage for v pp /wp program acceleration v cc = 2.7v 10% 11.5 12.5 v i pp current for v pp /wp program acceleration v cc = 2.7v 10% 15 ma v ol output low voltage i ol = 1.8ma 0.45 v v oh output high voltage i oh = ?100 av cc ?0.4 v v id identification voltage 11.5 12.5 v v lko (1) 1. sampled only, not 100% tested. program/erase lockout supply voltage 1.8 2.3 v
m29w640ft, m29w640fb dc and ac parameters 37/71 figure 8. read mode ac waveforms figure 9. page read ac waveforms ai05559 tavav tavqv taxqx telqx tehqz tglqv tglqx tghqx valid a0-a20/ a?1 g dq0-dq7/ dq8-dq15 e telqv tehqx tghqz valid tbhqv telbl/telbh tblqz byte ai11553 a2-a21 e g a0-a1 valid dq0-dq15 valid valid valid valid address valid data valid data valid data valid data tavqv1 tglqv tavqv telqv tehqx tehqz tghqx tghqz
dc and ac parameters m29w640ft, m29w640fb 38/71 table 14. read ac characteristics symbol alt parameter test condition m29w640ft, m29w640fb unit 60 70 t avav t rc address valid to ne xt address valid e = v il , g = v il min 60 70 ns t avqv t acc address valid to output valid e = v il , g = v il max 60 70 ns t avqv1 t pag e address valid to output valid (page) e = v il , g = v il max 25 25 ns t elqx (1) 1. sampled only, not 100% tested. t lz chip enable low to output transition g = v il min 0 0 ns t elqv t ce chip enable low to output valid g = v il max 60 70 ns t glqx (1) t olz output enable low to output transition e = v il min 0 0 ns t glqv t oe output enable low to output valid e = v il max 25 25 ns t ehqz (1) t hz chip enable high to output hi-z g = v il max 25 25 ns t ghqz (1) t df output enable high to output hi-z e = v il max 25 25 ns t ehqx t ghqx t axqx t oh chip enable, output enable or address transition to output transition min 0 0 ns t elbl t elbh t elfl t elfh chip enable to byte low or high max 5 5 ns t blqz t flqz byte low to output hi-z max 25 25 ns t bhqv t fhqv byte high to output valid max 30 30 ns
m29w640ft, m29w640fb dc and ac parameters 39/71 figure 10. write ac waveforms, write enable controlled ai05560 e g w a0-a20/ a?1 dq0-dq7/ dq8-dq15 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl rb twhrl
dc and ac parameters m29w640ft, m29w640fb 40/71 table 15. write ac characteristics, write enable controlled symbol alt parameter m29w640ft, m29w640fb unit 60 70 t avav t wc address valid to next address valid min 60 70 ns t elwl t cs chip enable low to write enable low min 0 0 ns t wlwh t wp write enable low to write enable high min 45 45 ns t dvwh t ds input valid to write enable high min 45 45 ns t whdx t dh write enable high to input transition min 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 ns t whwl t wph write enable high to write enable low min 30 30 ns t avwl t as address valid to write enable low min 0 0 ns t wlax t ah write enable low to address transition min 45 45 ns t ghwl output enable high to write enable low min 0 0 ns t whgl t oeh write enable high to output enable low min 0 0 ns t whrl (1) t busy program/erase valid to rb low max 30 30 ns t vchel t vcs v cc high to chip enable low min 50 50 s 1. sampled only, not 100% tested.
m29w640ft, m29w640fb dc and ac parameters 41/71 figure 11. write ac waveforms, chip enable controlled ai05561 e g w a0-a20/ a?1 dq0-dq7/ dq8-dq15 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel rb tehrl
dc and ac parameters m29w640ft, m29w640fb 42/71 figure 12. reset/block temporary unprotect ac waveforms table 16. write ac characteristics, chip enable controlled symbol alt parameter m29w640ft, m29w640fb unit 60 70 t avav t wc address valid to next address valid min 60 70 ns t wlel t ws write enable low to chip enable low min 0 0 ns t eleh t cp chip enable low to chip enable high min 45 45 ns t dveh t ds input valid to chip enable high min 45 45 ns t ehdx t dh chip enable high to input transition min 0 0 ns t ehwh t wh chip enable high to write enable high min 0 0 ns t ehel t cph chip enable high to chip enable low min 30 30 ns t avel t as address valid to chip enable low min 0 0 ns t elax t ah chip enable low to address transition min 45 45 ns t ghel output enable high chip enable low min 0 0 ns t ehgl t oeh chip enable high to output enable low min 0 0 ns t ehrl (1) t busy program/erase valid to rb low max 30 30 ns t vchwl t vcs v cc high to write enable low min 50 50 s 1. sampled only, not 100% tested. ai02931b rb w, rp tplpx tphwl, tphel, tphgl tplyh tphphh e, g trhwl, trhel, trhgl
m29w640ft, m29w640fb dc and ac parameters 43/71 figure 13. accelerated program timing waveforms ai05563 v pp /wp v pp v il or v ih tvhvpp tvhvpp table 17. reset/block temporary unprotect ac characteristics symbol alt parameter m29w640ft, m29w640fb unit t phwl (1) t phel t phgl (1) t rh rp high to write enable low, chip enable low, output enable low min 50 ns t rhwl (1) t rhel (1) t rhgl (1) t rb rb high to write enable low, chip enable low, output enable low min 0 ns t plpx t rp rp pulse width min 500 ns t plyh t ready rp low to read mode max 50 s t phphh (1) t vidr rp rise time to v id min 500 ns t vhvpp (1) v pp rise and fall time min 250 ns 1. sampled only, not 100% tested.
package mechanical m29w640ft, m29w640fb 44/71 8 package mechanical figure 14. tsop48 ? 48 lead plastic thin small outline, 12 x 20mm, top view package outline 1. drawing is not to scale. table 18. tsop48 ? 48 lead plastic thin small outline, 12 x 20mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.100 0.050 0.150 0. 0039 0.0020 0.0059 a2 1.000 0.950 1.050 0. 0394 0.0374 0.0413 b 0.220 0.170 0.270 0. 0087 0.0067 0.0106 c 0.100 0.210 0.0039 0.0083 cp 0.100 0.0039 d1 12.000 11.900 12.100 0.4724 0.4685 0.4764 e 20.000 19.800 20.200 0.7874 0.7795 0.7953 e1 18.400 18.300 18.500 0.7244 0.7205 0.7283 e 0.500 ? ? 0.0197 ? ? l 0.600 0.500 0.700 0. 0236 0.0197 0.0276 l1 0.800 0.0315 3 0 5 3 0 5 tsop-g b e die c l a1 e1 e a a2 1 24 48 25 d1 l1 cp
m29w640ft, m29w640fb package mechanical 45/71 figure 15. tfbga48 6x8mm - 6x8 active ball array, 0.8mm pitch, package outline 1. drawing is not to scale. table 19. tfbga48 6x8mm - 6x8 active ball array, 0.8mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.260 0.0102 a2 0.900 0.0354 b 0.350 0.450 0.0138 0.0177 d 6.000 5.900 6.100 0.2362 0.2323 0.2402 d1 4.000 ? ? 0.1575 ? ? ddd 0.100 0.0039 e 8.000 7.900 8.100 0.3150 0.3110 0.3189 e1 5.600 ? ? 0.2205 ? ? e 0.800 ? ? 0.0315 ? ? fd 1.000 ? ? 0.0394 ? ? fe 1.200 ? ? 0.0472 ? ? sd 0.400 ? ? 0.0157 ? ? se 0.400 ? ? 0.0157 ? ? e1 e d1 d eb a2 a1 a bga-z32 ddd fd fe sd se e ball "a1"
part numbering m29w640ft, m29w640fb 46/71 9 part numbering note: this product is also available with the extended block factory locked. for further details and ordering information contact your nearest st sales office. devices are shipped from the factory with the memory content bits erased to 1. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 20. ordering information scheme example: m29w640fb 70 n 6 f device type m29 operating voltage w = v cc = 2.7 to 3.6v device function 640f = 64 mbit (x8 / x16), boot block array matrix t = top boot b = bottom boot speed 60 = 60ns 70 = 70ns package n = tsop48: 12 x 20 mm za = tfbga48: 6x8mm, 0.80 mm pitch temperature range 6 = ? 40 to 85 c option e = ecopack package, standard packing f = ecopack package, tape & reel packing
m29w640ft, m29w640fb block addresses 47/71 appendix a block addresses table 21. top boot block addresses, m29w640ft block kbytes/kwords protection block group (x8) (x16) 0 64/32 protection group 000000h?00ffffh (1) 000000h?007fffh (1) 1 64/32 010000h?01ff ffh 008000h?00ffffh 2 64/32 020000h?02ffffh 010000h?017fffh 3 64/32 030000h?03ff ffh 018000h?01ffffh 4 64/32 protection group 040000h?04ffffh 020000h?027fffh 5 64/32 050000h?05ff ffh 028000h?02ffffh 6 64/32 060000h?06ffffh 030000h?037fffh 7 64/32 070000h?07ff ffh 038000h?03ffffh 8 64/32 protection group 080000h?08ffffh 040000h?047fffh 9 64/32 090000h?09ff ffh 048000h?04ffffh 10 64/32 0a0000h?0affffh 050000h?057fffh 11 64/32 0b0000h?0bffffh 058000h?05ffffh 12 64/32 protection group 0c0000h?0cffffh 060000h?067fffh 13 64/32 0d0000h?0dffffh 068000h?06ffffh 14 64/32 0e0000h?0effffh 070000h?077fffh 15 64/32 0f0000h?0fff ffh 078000h?07ffffh 16 64/32 protection group 100000h?10ffffh 080000h?087fffh 17 64/32 110000h?11ff ffh 088000h?08ffffh 18 64/32 120000h?12ffffh 090000h?097fffh 19 64/32 130000h?13ff ffh 098000h?09ffffh 20 64/32 protection group 140000h?14ffffh 0a0000h?0a7fffh 21 64/32 150000h?15ffff h 0a8000h?0affffh 22 64/32 160000h?16ffff h 0b0000h?0b7fffh 23 64/32 170000h?17ffff h 0b8000h?0bffffh 24 64/32 protection group 180000h?18ffffh 0c0000h?0c7fffh 25 64/32 190000h?19ffffh 0c8000h?0cffffh 26 64/32 1a0000h?1affffh 0d0000h?0d7fffh 27 64/32 1b0000h?1bffffh 0d8000h?0dffffh 28 64/32 protection group 1c0000h?1cffffh 0e0000h?0e7fffh 29 64/32 1d0000h?1dffffh 0e8000h?0effffh 30 64/32 1e0000h?1effffh 0f0000h?0f7fffh 31 64/32 1f0000h?1fffffh 0f8000h?0fffffh
block addresses m29w640ft, m29w640fb 48/71 32 64/32 protection group 200000h?20ffffh 100000h?107fffh 33 64/32 210000h?21ff ffh 108000h?10ffffh 34 64/32 220000h?22ffffh 110000h?117fffh 35 64/32 230000h?23ff ffh 118000h?11ffffh 36 64/32 protection group 240000h?24ffffh 120000h?127fffh 37 64/32 250000h?25ff ffh 128000h?12ffffh 38 64/32 260000h?26ffffh 130000h?137fffh 39 64/32 270000h?27ff ffh 138000h?13ffffh 40 64/32 protection group 280000h?28ffffh 140000h?147fffh 41 64/32 290000h?29ff ffh 148000h?14ffffh 42 64/32 2a0000h?2affffh 150000h?157fffh 43 64/32 2b0000h?2bffffh 158000h?15ffffh 44 64/32 protection group 2c0000h?2cffffh 160000h?167fffh 45 64/32 2d0000h?2dffffh 168000h?16ffffh 46 64/32 2e0000h?2effffh 170000h?177fffh 47 64/32 2f0000h?2fff ffh 178000h?17ffffh 48 64/32 protection group 300000h?30ffffh 180000h?187fffh 49 64/32 310000h?31ff ffh 188000h?18ffffh 50 64/32 320000h?32ffffh 190000h?197fffh 51 64/32 330000h?33ff ffh 198000h?19ffffh 52 64/32 protection group 340000h?34ffffh 1a0000h?1a7fffh 53 64/32 350000h?35ffff h 1a8000h?1affffh 54 64/32 360000h?36ffff h 1b0000h?1b7fffh 55 64/32 370000h?37ffff h 1b8000h?1bffffh 56 64/32 protection group 380000h?38ffffh 1c0000h?1c7fffh 57 64/32 390000h?39ffffh 1c8000h?1cffffh 58 64/32 3a0000h?3affffh 1d0000h?1d7fffh 59 64/32 3b0000h?3bffffh 1d8000h?1dffffh 60 64/32 protection group 3c0000h?3cffffh 1e0000h?1e7fffh 61 64/32 3d0000h?3dffffh 1e8000h?1effffh 62 64/32 3e0000h?3effffh 1f0000h?1f7fffh 63 64/32 3f0000h?3fffffh 1f8000h?1fffffh table 21. top boot block addresses, m29w640ft (continued) block kbytes/kwords protection block group (x8) (x16)
m29w640ft, m29w640fb block addresses 49/71 64 64/32 protection group 400000h?40ffffh 200000h?207fffh 65 64/32 410000h?41ff ffh 208000h?20ffffh 66 64/32 420000h?42ffffh 210000h?217fffh 67 64/32 430000h?43ff ffh 218000h?21ffffh 68 64/32 protection group 440000h?44ffffh 220000h?227fffh 69 64/32 450000h?45ff ffh 228000h?22ffffh 70 64/32 460000h?46ffffh 230000h?237fffh 71 64/32 470000h?47ff ffh 238000h?23ffffh 72 64/32 protection group 480000h?48ffffh 240000h?247fffh 73 64/32 490000h?49ff ffh 248000h?24ffffh 74 64/32 4a0000h?4affffh 250000h?257fffh 75 64/32 4b0000h?4bffffh 258000h?25ffffh 76 64/32 protection group 4c0000h?4cffffh 260000h?267fffh 77 64/32 4d0000h?4dffffh 268000h?26ffffh 78 64/32 4e0000h?4effffh 270000h?277fffh 79 64/32 4f0000h?4fff ffh 278000h?27ffffh 80 64/32 protection group 500000h?50ffffh 280000h?287fffh 81 64/32 510000h?51ff ffh 288000h?28ffffh 82 64/32 520000h?52ffffh 290000h?297fffh 83 64/32 530000h?53ff ffh 298000h?29ffffh 84 64/32 protection group 540000h?54ffffh 2a0000h?2a7fffh 85 64/32 550000h?55ffff h 2a8000h?2affffh 86 64/32 560000h?56ffff h 2b0000h?2b7fffh 87 64/32 570000h?57ffff h 2b8000h?2bffffh 88 64/32 protection group 580000h?58ffffh 2c0000h?2c7fffh 89 64/32 590000h?59ffffh 2c8000h?2cffffh 90 64/32 5a0000h?5affffh 2d0000h?2d7fffh 91 64/32 5b0000h?5bffffh 2d8000h?2dffffh 92 64/32 protection group 5c0000h?5cffffh 2e0000h?2e7fffh 93 64/32 5d0000h?5dffffh 2e8000h?2effffh 94 64/32 5e0000h?5effffh 2f0000h?2f7fffh 95 64/32 5f0000h?5fffffh 2f8000h?2fffffh table 21. top boot block addresses, m29w640ft (continued) block kbytes/kwords protection block group (x8) (x16)
block addresses m29w640ft, m29w640fb 50/71 96 64/32 protection group 600000h?60ffffh 300000h?307fffh 97 64/32 610000h?61ff ffh 308000h?30ffffh 98 64/32 620000h?62ffffh 310000h?317fffh 99 64/32 630000h?63ff ffh 318000h?31ffffh 100 64/32 protection group 640000h?64ffffh 320000h?327fffh 101 64/32 650000h?65ff ffh 328000h?32ffffh 102 64/32 660000h?66ffffh 330000h?337fffh 103 64/32 670000h?67ff ffh 338000h?33ffffh 104 64/32 protection group 680000h?68ffffh 340000h?347fffh 105 64/32 690000h?69ff ffh 348000h?34ffffh 106 64/32 6a0000h?6affffh 350000h?357fffh 107 64/32 6b0000h?6bffffh 358000h?35ffffh 108 64/32 protection group 6c0000h?6cffffh 360000h?367fffh 109 64/32 6d0000h?6dffffh 368000h?36ffffh 110 64/32 6e0000h?6effffh 370000h?377fffh 111 64/32 6f0000h?6fff ffh 378000h?37ffffh 112 64/32 protection group 700000h?70ffffh 380000h?387fffh 113 64/32 710000h?71ff ffh 388000h?38ffffh 114 64/32 720000h?72ffffh 390000h?397fffh 115 64/32 730000h?73ff ffh 398000h?39ffffh 116 64/32 protection group 740000h?74ffffh 3a0000h?3a7fffh 117 64/32 750000h?75ffff h 3a8000h?3affffh 118 64/32 760000h?76ffff h 3b0000h?3b7fffh 119 64/32 770000h?77ffff h 3b8000h?3bffffh 120 64/32 protection group 780000h?78ffffh 3c0000h?3c7fffh 121 64/32 790000h?79ffffh 3c8000h?3cffffh 122 64/32 7a0000h?7affffh 3d0000h?3d7fffh 123 64/32 7b0000h?7bffffh 3d8000h?3dffffh table 21. top boot block addresses, m29w640ft (continued) block kbytes/kwords protection block group (x8) (x16)
m29w640ft, m29w640fb block addresses 51/71 124 64/32 protection group 7c0000h?7cffffh 3e0000h?3e7fffh 125 64/32 7d0000h?7dffffh 3e8000h?3effffh 126 64/32 7e0000h?7effffh 3f0000h?3f7fffh 127 8/4 7f0000h?7f1fff h 3f8000h?3f8fffh 128 8/4 7f2000h?7f3fff h 3f9000h?3f9fffh 129 8/4 7f4000h?7f5fffh 3fa000h?3fafffh 130 8/4 7f6000h?7f7fff h 3fb000h?3fbfffh 131 8/4 7f8000h?7f9fff h 3fc000h?3fcfffh 132 8/4 7fa000h?7fbfffh 3fd000h?3fdfffh 133 8/4 7fc000h?7fdfff h 3fe000h?3fefffh 134 8/4 7fe000h?7ffff fh 3ff000h?3fffffh 1. used as the extended block addr esses in extended block mode. table 21. top boot block addresses, m29w640ft (continued) block kbytes/kwords protection block group (x8) (x16)
block addresses m29w640ft, m29w640fb 52/71 table 22. bottom boot block addresses, m29w640fb block kbytes/kwords protection block group (x8) (x16) 08/4 protection group 000000h-001fffh (1) 000000h?000fffh (1) 1 8/4 002000h-003fffh 001000h?001fffh 2 8/4 004000h-005fffh 002000h?002fffh 3 8/4 006000h-007fffh 003000h?003fffh 4 8/4 008000h-009fffh 004000h?004fffh 5 8/4 00a000h-00bfffh 005000h?005fffh 6 8/4 00c000h-00dfffh 006000h?006fffh 7 8/4 00e000h-00ffffh 007000h?007fffh 8 64/32 010000h-01ffffh 008000h?00ffffh 9 64/32 020000h-02ff ffh 010000h?017fffh 10 64/32 030000h-03ffffh 018000h?01ffffh 11 64/32 protection group 040000h-04ffffh 020000h?027fffh 12 64/32 050000h-05ffffh 028000h?02ffffh 13 64/32 060000h-06ff ffh 030000h?037fffh 14 64/32 070000h-07ffffh 038000h?03ffffh 15 64/32 protection group 080000h-08ffffh 040000h?047fffh 16 64/32 090000h-09ffffh 048000h?04ffffh 17 64/32 0a0000h-0affffh 050000h?057fffh 18 64/32 0b0000h-0bffffh 058000h?05ffffh 19 64/32 protection group 0c0000h-0cffffh 060000h?067fffh 20 64/32 0d0000h-0dffffh 068000h?06ffffh 21 64/32 0e0000h-0effffh 070000h?077fffh 22 64/32 0f0000h-0fff ffh 078000h?07ffffh 23 64/32 protection group 100000h-10ffffh 080000h?087fffh 24 64/32 110000h-11ffffh 088000h?08ffffh 25 64/32 120000h-12ff ffh 090000h?097fffh 26 64/32 130000h-13ffffh 098000h?09ffffh 27 64/32 protection group 140000h-14ffffh 0a0000h?0a7fffh 28 64/32 150000h-15ffffh 0a8000h?0affffh 29 64/32 160000h-16ff ffh 0b0000h?0b7fffh 30 64/32 170000h-17ffffh 0b8000h?0bffffh 31 64/32 protection group 180000h-18ffffh 0c0000h?0c7fffh 32 64/32 190000h-19ffffh 0c8000h?0cffffh 33 64/32 1a0000h-1affffh 0d0000h?0d7fffh 34 64/32 1b0000h-1bffffh 0d8000h?0dffffh
m29w640ft, m29w640fb block addresses 53/71 35 64/32 protection group 1c0000h-1cffffh 0e0000h?0e7fffh 36 64/32 1d0000h-1dffffh 0e8000h?0effffh 37 64/32 1e0000h-1effffh 0f0000h?0f7fffh 38 64/32 1f0000h-1fff ffh 0f8000h?0fffffh 39 64/32 protection group 200000h-20ffffh 100000h?107fffh 40 64/32 210000h-21ffffh 108000h?10ffffh 41 64/32 220000h-22ff ffh 110000h?117fffh 42 64/32 230000h-23ffffh 118000h?11ffffh 43 64/32 protection group 240000h-24ffffh 120000h?127fffh 44 64/32 250000h-25ffffh 128000h?12ffffh 45 64/32 260000h-26ff ffh 130000h?137fffh 46 64/32 270000h-27ffffh 138000h?13ffffh 47 64/32 protection group 280000h-28ffffh 140000h?147fffh 48 64/32 290000h-29ffffh 148000h?14ffffh 49 64/32 2a0000h-2affffh 150000h?157fffh 50 64/32 2b0000h-2bffffh 158000h?15ffffh 51 64/32 protection group 2c0000h-2cffffh 160000h?167fffh 52 64/32 2d0000h-2dffffh 168000h?16ffffh 53 64/32 2e0000h-2effffh 170000h?177fffh 54 64/32 2f0000h-2fff ffh 178000h?17ffffh 55 64/32 protection group 300000h-30ffffh 180000h?187fffh 56 64/32 310000h-31ffffh 188000h?18ffffh 57 64/32 320000h-32ff ffh 190000h?197fffh 58 64/32 330000h-33ffffh 198000h?19ffffh 59 64/32 protection group 340000h-34ffffh 1a0000h?1a7fffh 60 64/32 350000h-35ffffh 1a8000h?1affffh 61 64/32 360000h-36ff ffh 1b0000h?1b7fffh 62 64/32 370000h-37ffffh 1b8000h?1bffffh 63 64/32 protection group 380000h-38ffffh 1c0000h?1c7fffh 64 64/32 390000h-39ffffh 1c8000h?1cffffh 65 64/32 3a0000h-3affffh 1d0000h?1d7fffh 66 64/32 3b0000h-3bffffh 1d8000h?1dffffh table 22. bottom boot block addresses, m29w640fb (continued) block kbytes/kwords protection block group (x8) (x16)
block addresses m29w640ft, m29w640fb 54/71 67 64/32 protection group 3c0000h-3cffffh 1e0000h?1e7fffh 68 64/32 3d0000h-3dffffh 1e8000h?1effffh 69 64/32 3e0000h-3effffh 1f0000h?1f7fffh 70 64/32 3f0000h-3fff ffh 1f8000h?1fffffh 71 64/32 protection group 400000h-40ffffh 200000h?207fffh 72 64/32 410000h-41ffffh 208000h?20ffffh 73 64/32 420000h-42ff ffh 210000h?217fffh 74 64/32 430000h-43ffffh 218000h?21ffffh 75 64/32 protection group 440000h-44ffffh 220000h?227fffh 76 64/32 450000h-45ffffh 228000h?22ffffh 77 64/32 460000h-46ff ffh 230000h?237fffh 78 64/32 470000h-47ffffh 238000h?23ffffh 79 64/32 protection group 480000h-48ffffh 240000h?247fffh 80 64/32 490000h-49ffffh 248000h?24ffffh 81 64/32 4a0000h-4affffh 250000h?257fffh 82 64/32 4b0000h-4bffffh 258000h?25ffffh 83 64/32 protection group 4c0000h-4cffffh 260000h?267fffh 84 64/32 4d0000h-4dffffh 268000h?26ffffh 85 64/32 4e0000h-4effffh 270000h?277fffh 86 64/32 4f0000h-4fff ffh 278000h?27ffffh 87 64/32 protection group 500000h-50ffffh 280000h?287fffh 88 64/32 510000h-51ffffh 288000h?28ffffh 89 64/32 520000h-52ff ffh 290000h?297fffh 90 64/32 530000h-53ffffh 298000h?29ffffh 91 64/32 protection group 540000h-54ffffh 2a0000h?2a7fffh 92 64/32 550000h-55ffffh 2a8000h?2affffh 93 64/32 560000h-56ff ffh 2b0000h?2b7fffh 94 64/32 570000h-57ffffh 2b8000h?2bffffh 95 64/32 protection group 580000h-58ffffh 2c0000h?2c7fffh 96 64/32 590000h-59ffffh 2c8000h?2cffffh 97 64/32 5a0000h-5affffh 2d0000h?2d7fffh 98 64/32 5b0000h-5bffffh 2d8000h?2dffffh table 22. bottom boot block addresses, m29w640fb (continued) block kbytes/kwords protection block group (x8) (x16)
m29w640ft, m29w640fb block addresses 55/71 99 64/32 protection group 5c0000h-5cffffh 2e0000h?2e7fffh 100 64/32 5d0000h-5dffffh 2e8000h?2effffh 101 64/32 5e0000h-5effffh 2f0000h?2f7fffh 102 64/32 5f0000h-5fff ffh 2f8000h?2fffffh 103 64/32 protection group 600000h-60ffffh 300000h?307fffh 104 64/32 610000h-61ffffh 308000h?30ffffh 105 64/32 620000h-62ff ffh 310000h?317fffh 106 64/32 630000h-63ffffh 318000h?31ffffh 107 64/32 protection group 640000h-64ffffh 320000h?327fffh 108 64/32 650000h-65ffffh 328000h?32ffffh 109 64/32 660000h-66ff ffh 330000h?337fffh 110 64/32 670000h-67ffffh 338000h?33ffffh 111 64/32 protection group 680000h-68ffffh 340000h?347fffh 112 64/32 690000h-69ffffh 348000h?34ffffh 113 64/32 6a0000h-6affffh 350000h?357fffh 114 64/32 6b0000h-6bffffh 358000h?35ffffh 115 64/32 protection group 6c0000h-6cffffh 360000h?367fffh 116 64/32 6d0000h-6dffffh 368000h?36ffffh 117 64/32 6e0000h-6effffh 370000h?377fffh 118 64/32 6f0000h-6fff ffh 378000h?37ffffh 119 64/32 protection group 700000h-70ffffh 380000h?387fffh 120 64/32 710000h-71ffffh 388000h?38ffffh 121 64/32 720000h-72ff ffh 390000h?397fffh 122 64/32 730000h-73ffffh 398000h?39ffffh 123 64/32 protection group 740000h-74ffffh 3a0000h?3a7fffh 124 64/32 750000h-75ffffh 3a8000h?3affffh 125 64/32 760000h-76ff ffh 3b0000h?3b7fffh 126 64/32 770000h-77ffffh 3b8000h?3bffffh 127 64/32 protection group 780000h-78ffffh 3c0000h?3c7fffh 128 64/32 790000h-79ffffh 3c8000h?3cffffh 129 64/32 7a0000h-7affffh 3d0000h?3d7fffh 130 64/32 7b0000h-7bffffh 3d8000h?3dffffh table 22. bottom boot block addresses, m29w640fb (continued) block kbytes/kwords protection block group (x8) (x16)
block addresses m29w640ft, m29w640fb 56/71 131 64/32 protection group 7c0000h-7cffffh 3e0000h?3e7fffh 132 64/32 7d0000h-7dffffh 3e8000h?3effffh 133 64/32 7e0000h-7effffh 3f0000h?3f7fffh 134 64/32 7f0000h-7fff ffh 3f8000h?3fffffh 1. used as the extended block addr esses in extended block mode. table 22. bottom boot block addresses, m29w640fb (continued) block kbytes/kwords protection block group (x8) (x16)
m29w640ft, m29w640fb common flash interface (cfi) 57/71 appendix b common flash interface (cfi) the common flash interface is a jedec approved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing pa rameters, density information and functions supported by the memory. the system can interface easily with the device, enabling the software to upgrade itself when necessary. when the cfi query command is issued the device enters cfi query mode and the data structure is read from the memory. tables 23 , 24 , 25 , 26 , 27 , and 28 , show the addresses used to retrieve the data. the cfi data structure also contains a security area where a 64 bit unique security number is written (see table 28: security code area ). this area can be accessed only in read mode by the final user. it is impossible to change the security number after it has been written by st. table 23. query structure overview (1) 1. query data are always present ed on the lowest order data outputs. address sub-section name description x16 x8 10h 20h cfi query identification string comm and set id and algorithm data offset 1bh 36h system interface information device timing & voltage information 27h 4eh device geometry definition flash device layout 40h 80h primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) 61h c2h security code area 64 bit unique device number
common flash interface (cfi) m29w640ft, m29w640fb 58/71 table 24. cfi query identification string (1) 1. query data are always presented on the lowest order data outputs (dq7-dq0) only. dq8-dq15 are ?0?. address data description value x16 x8 10h 20h 0051h ?q? 11h 22h 0052h query unique ascii string "qry" "r" 12h 24h 0059h "y" 13h 26h 0002h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm amd compatible 14h 28h 0000h 15h 2ah 0040h address for primary algorithm extended query table (see ta b l e 2 7 ) p = 40h 16h 2ch 0000h 17h 2eh 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 18h 30h 0000h 19h 32h 0000h address for alternate algorithm extended query table na 1ah 34h 0000h table 25. cfi query system interface information address data description value x16 x8 1bh 36h 0027h v cc logic supply minimum program/erase voltage bit 7 to 4bcd value in volts bit 3 to 0bcd value in 100 mv 2.7v 1ch 38h 0036h v cc logic supply maximum program/erase voltage bit 7 to 4bcd value in volts bit 3 to 0bcd value in 100 mv 3.6v 1dh 3ah 00b5h v pp [programming] supply minimum program/erase voltage bit 7 to 4hex value in volts bit 3 to 0bcd value in 100 mv 11.5v 1eh 3ch 00c5h v pp [programming] supply maximum program/erase voltage bit 7 to 4hex value in volts bit 3 to 0bcd value in 100 mv 12.5v 1fh 3eh 0004h typical timeout per single byte/word program = 2 n s 16s 20h 40h 0000h typical timeout for minimum size write buffer program = 2 n s na 21h 42h 000ah typical timeout per individual block erase = 2 n ms 1s 22h 44h 0000h typical timeout for full chip erase = 2 n ms na 23h 46h 0004h maximum timeout for byte/word program = 2 n times typical 256s 24h 48h 0000h maximum timeout for write buffer program = 2 n times typical na 25h 4ah 0003h maximum timeout per individual block erase = 2 n times typical 8s 26h 4ch 0000h maximum timeout for chip erase = 2 n times typical na
m29w640ft, m29w640fb common flash interface (cfi) 59/71 table 26. device geometry definition (1) 1. for bottom boot devices, erase block region 1 is located from address 000000h to 007fffh and erase block region 2 from address 008000h to 3fffffh. for top boot devices, erase block region 1 is located from address 000000h to 3f7fffh and erase block region 2 from address 3f8000h to 3fffffh. address data description value x16 x8 27h 4eh 0017h device size = 2 n in number of bytes 8 mbyte 28h 29h 50h 52h 0002h 0000h flash device interface code description x8, x16 async. 2ah 2bh 54h 56h 0004h 0000h maximum number of bytes in multi-byte program or page = 2 n 16 bytes 2ch 58h 0002h number of erase block regions. it specifies the number of regions containing contiguous erase blocks of the same size. 2 2dh 2eh 5ah 5ch 0007h 0000h region 1 information number of erase blocks of identical size = 0007h+1 8 2fh 30h 5eh 60h 0020h 0000h region 1 information block size in region 1 = 0020h * 256 byte 8kbyte 31h 32h 62h 64h 007eh 0000h region 2 information number of erase blocks of identical size= 007eh+1 127 33h 34h 66h 68h 0000h 0001h region 2 information block size in region 2 = 0100h * 256 byte 64kbyte 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h region 3 information number of erase blocks of identical size=007fh+1 region 3 information block size in region 3 = 0000h * 256 byte 0 0 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h region 4 information number of erase blocks of identical size=007fh+1 region 4 information block size in region 4 = 0000h * 256 byte 0 0
common flash interface (cfi) m29w640ft, m29w640fb 60/71 table 27. primary algorithm-specific extended query table address data description value x16 x8 40h 80h 0050h primary algorithm extended query table unique ascii string ?pri? "p" 41h 82h 0052h "r" 42h 84h 0049h "i" 43h 86h 0031h major version number, ascii ?1? 44h 88h 0033h minor version number, ascii "3" 45h 8ah 0000h address sensitive unlock (bits 1 to 0) 00h = required, 01h = not required silicon revision number (bits 7 to 2) ye s 46h 8ch 0002h erase suspend 00h = not supported, 01h = read only, 02 = read and write 2 47h 8eh 0004h block protection 00h = not supported, x = number of blocks per protection group 4 48h 90h 0001h temporary block unprotect 00h = not supported, 01h = supported ye s 49h 92h 0004h block protect /unprotect 04 = m29w640f 04 4ah 94h 0000h simultaneous operat ions, 00h = not supported no 4bh 96h 0000h burst mode: 00h = not supported, 01h = supported no 4ch 98h 0001h page mode: 00h = not supported, 01h = 4 page word, 02h = 8 page word ye s 4dh 9ah 00b5h v pp supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 11.5v 4eh 9ch 00c5h v pp supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 12.5v 4fh 9eh 0002h 0003h top/bottom boot block flag 02h = bottom boot device 03h = top boot device ? 50h a0h 0001h program suspend 00h = not supported 01h = supported suppor ted
m29w640ft, m29w640fb common flash interface (cfi) 61/71 table 28. security code area address data description x16 x8 61h c3h, c2h xxxx 64 bit: unique device number 62h c5h, c4h xxxx 63h c7h, c6h xxxx 64h c9h, c8h xxxx
extended memory block m29w640ft, m29w640fb 62/71 appendix c extended memory block the m29w640f has an extra block, the extend ed block, that can be accessed using a dedicated command. this extended block is 128 words in x16 mode and 256 bytes in x8 mode. it is used as a security block to provide a permanent security identification number) or to store additional information. the extended block is either factory locked or customer lockable, its status is indicated by bit dq7. this bit is permanently set to either ?1? or ?0? at the factory and cannot be changed. when set to ?1?, it indicates that the device is factory locked and the extended block is protected. when set to ?0?, it indicates that the device is customer lockable and the extended block is unprotected. bit dq7 being permanently locked to either ?1? or ?0? is another security feature which ensures that a customer lockable device cannot be used instead of a factory locked one. bit dq7 is the most significant bit in the extended block verify code and a specific procedure must be followed to read it. see ?extended memory block verify code ? in ta b l e 4 : bus operations, byte = v il and table 5: bus operations, byte = v ih , for details of how to read bit dq7. the extended block can only be accessed when the device is in extended block mode. for details of how the extended block mode is entered and exited, refer to the section 4.3.1: enter extended block command and section 4.3.2: exit extended block command , and to ta bl e 6 and table 7: commands, 8-bit mode, byte = v il . c.1 factory locked extended block in devices where the extended block is factory locked, the security identification number is written to the extended block address space (see table 29: extended block address and data ) in the factory. the dq7 bit is set to ?1? and the extended block cannot be unprotected. c.2 customer lockable extended block a device where the extended block is customer lockable is delivered with the dq7 bit set to ?0? and the extended block unprotected. it is up to the customer to program and protect the extended block but care must be taken because the protection of the extended block is not reversible. there are two ways of protecting the extended block: issue the enter extended block command to place the device in extended block mode, then use the in-system technique with rp either at v ih or at v id (refer to appendix d , section d.2: in-system technique and to the corresponding flowcharts, figure 18 and figure 19 , for a detailed explanation of the technique). issue the enter extended block command to place the device in extended block mode, then use the programmer technique (refer to appendix d , section d.1: programmer technique and to the corresponding flowcharts, figure 16 and figure 17 , for a detailed explanation of the technique). once the extended block is programmed and protected, the exit extended block command must be issued to exit the extended block mode and return the device to read mode.
m29w640ft, m29w640fb extended memory block 63/71 table 29. extended block address and data address data x8 x16 factory locked customer lockable 000000h-00007fh 000000h-00003fh sec urity identification number determined by customer 000080h-0000ffh 000040h-00007fh unavailable
block protection m29w640ft, m29w640fb 64/71 appendix d block protection block protection can be used to prevent any operation from modifying the data stored in the memory. the blocks are protected in groups, refer to appendix a: block addresses , ta bl e 2 1 and ta b l e 2 2 for details of the protection groups. once protected, program and erase operations within the protected group fail to change the data. there are three techniques that can be used to control block protection, these are the programmer technique, the in-system technique and temporary unprotection. temporary unprotection is controlled by the reset/block temporary unprotection pin, rp ; this is described in the signal descriptions section. d.1 programmer technique the programmer technique uses high (v id ) voltage levels on some of the bus pins. these cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in programming equipment. to protect a group of blocks follow the flowchart in figure 16: programmer equipment group protect flowchart . to unprotect the whole chip it is necessary to protect all of the groups first, then all groups can be unprotected at the same time. to unprotect the chip follow figure 17: programmer equipment chip unprotect flowchart . table 30: programmer technique bus operations, byte = v ih or v il , gives a summary of each operation. the timing on these flowcharts is critical. care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. do not abort the procedure before reaching the end. chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. d.2 in-system technique the in-system technique requires a high voltage level on the reset/blocks temporary unprotect pin, rp (1) . this can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the memory has been fitted to the system. to protect a group of blocks follow the flowchart in figure 18: in-system equipment group protect flowchart . to unprotect the whole chip it is necessary to protect all of the groups first, then all the groups can be unprotected at the same time. to unprotect the chip follow figure 19: in-system equipment chip unprotect flowchart . the timing on these flowcharts is critical. care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. do not allow the microprocessor to service interrupts that will upset the timing a nd do not abort the proc edure before reaching the end. chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. note: rp can be either at v ih or at v id when using the in-system technique to protect the extended block.
m29w640ft, m29w640fb block protection 65/71 table 30. programmer technique bus operations, byte = v ih or v il operation e g w address inputs a0-a21 data inputs/outputs dq15a?1, dq14-dq0 block (group) protect (1) v il v id v il pulse a9 = v id , a12-a21 = block address others = x x chip unprotect v id v id v il pulse a9 = v id , a12 = v ih , a15 = v ih others = x x block (group) protection verify v il v il v ih a0, a2, a3 = v il , a1 = v ih , a6 = v il , a9 = v id , a12-a21 = block address others = x pass = xx01h retry = xx00h block (group) unprotection verify v il v il v ih a0, a2, a3 = v il , a1 = v ih , a6 = v ih , a9 = v id , a12-a21 = block address others = x retry = xx01h pass = xx00h 1. block protection groups are shown in appendix a , tables 21 and 22 .
block protection m29w640ft, m29w640fb 66/71 figure 16. programmer equipment group protect flowchart 1. block protection groups are shown in appendix a , tables 21 and 22 . address = group address ai11555 g, a9 = v id , e = v il n = 0 wait 4s wait 100s w = v il w = v ih e, g = v ih , a0, a2, a3 = v il , a1 =v ih , a6 =v il, a9 = vid, others = x a9 = v ih e, g = v ih ++n = 25 start fail pass yes no data = 01h yes no w = v ih e = v il wait 4s g = v il wait 60ns read data verify protect set-up end a9 = v ih e, g = v ih
m29w640ft, m29w640fb block protection 67/71 figure 17. programmer equipment chip unprotect flowchart 1. block protection groups are shown in appendix a , tables 21 and 22 . protect all groups ai11556b a6, a12, a15 = v ih (1) e, g, a9 = v id data w = v ih e, g = v ih address = current group address a0, a2, a3 = v il , a1 =v ih , a6 =v ih, a9 = vid, others = x wait 10ms = 00h increment current group n = 0 current group = 0 wait 4s w = v il ++n = 1000 start yes yes no no last group yes no e = v il wait 4s g = v il wait 60ns read data fail pass verify unprotect set-up end a9 = v ih e, g = v ih a9 = v ih e, g = v ih
block protection m29w640ft, m29w640fb 68/71 figure 18. in-system equipment group protect flowchart 1. block protection groups are shown in appendix a , tables 21 and 22 . 2. rp can be either at v ih or at v id when using the in-system techni que to protect the extended block. ai11563 write 60h address = group address a0, a2, a3, a6 = v il , a1 = v ih n = 0 wait 100s write 40h address = group address a0, a2, a3, a6 = v il , a1 = v ih rp = v ih ++n = 25 start fail pass yes no data = 01h yes no rp = v ih wait 4s verify protect set-up end read data address = group address a0, a2, a3, a6 = v il , a1 = v ih rp = v id issue read/reset command issue read/reset command write 60h address = group address a0, a2, a3, a6 = v il , a1 = v ih
m29w640ft, m29w640fb block protection 69/71 figure 19. in-system equipment chip unprotect flowchart 1. block protection groups are shown in appendix a , tables 21 and 22 . ai11564 write 60h any address with a0, a2, a3 = v il , a1, a6 = v ih n = 0 current group = 0 wait 10ms write 40h address = current group address a0, a2, a3 = v il , a1, a6 = v ih rp = v ih ++n = 1000 start fail pass yes no data = 00h yes no rp = v ih wait 4s read data address = current group address a0, a2, a3 = v il , a1, a6 = v ih rp = v id issue read/reset command issue read/reset command protect all groups increment current group last group yes no write 60h any address with a0, a2, a3, a6 = v il , a1 = v ih verify unprotect set-up end
revision history m29w640ft, m29w640fb 70/71 revision history table 31. document revision history date revision changes 01-mar-2005 0.1 first issue. 17-may-2005 0.2 asynchronous page mode added. 70ns speed class added. 07-oct-2005 1.0 device codes modified. tfbga63 replaced by tfbga48 6x8 package. ecopack text updated page size changed to 4 word. 90ns speed class removed. quadruple word/octuple byte program command added. table 4: bus operations, byte = v il and table 5: bus operations, byte = v ih : a0-a21 addresses for reading the device code, the manufacturer code, the extended memory block verify code, and the block protection status, have been updated. appendix d: block protection : table 30: programmer technique bus operations, byte = v ih or v il : a0-a21 addresses updated for block protection/unprotection verify using the programmer technique. 02-dec-2005 2 datasheet status changed to ?full datasheet?. 60ns speed class added. program suspend and resume added. section 2.8: v pp /write protect (v pp/ wp) and section 4.2: fast program commands . section 4: command interface restructured. table 29: extended block address and data updated. 15-dec-2005 3 double byte program commands added in section 4: command interface . table 4: bus operations, byte = v il and table 5: bus operations, byte = v ih .: a6 changed from v ih to v il for read block protection status operation. 10-mar-2006 4 dq7 changed to dq7 for program, program during erase suspend and program error in table 9: status register bits . a6 = v il corrected to a6 = v ih during the verify phase in figure 17: programmer equipment chip unprotect flowchart . address ranges modified for x8 and x16 modes in table 29: extended block address and data . 23-aug-2006 5 amended mistake in second title (m29w640ft changed to m29w640fb); removed the 4th cycle fr om the double byte program of table 7: commands, 8-bit mode, byte = v il 25-oct-2006 6 table 9: status register bits updated. 10-dec-2007 7 applied numonyx branding.
m29w640ft, m29w640fb 71/71 please read carefully: information in this document is provided in connection with numonyx? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in numonyx's terms and conditions of sale for such products, numonyx assumes no liability whatsoever, and numonyx disclaims any express or implied warranty, relating to sale and/or use of numonyx products including liability or warranties re lating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in n uclear facility applications. numonyx may make changes to specifications and product descriptions at any time, without notice. numonyx, b.v. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights th at relate to the presented subject matter. the furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? num onyx reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. contact your local numonyx sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an order number and are referenced in this document, or other numonyx literature may be obtained by visiting numonyx's website at http://www.numonyx.com . numonyx strataflash is a trademark or registered trademark of numonyx or its subsidiaries in the united states and other countr ies. *other names and brands may be claimed as the property of others. copyright ? 11/5/7, numonyx, b.v., all rights reserved.

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